Fan-out wafer level packaging process

As the light and thin have become the direction of the development of consumer electronics, it is becoming more and more common to eliminate the materials and processes and to reduce the size of the wafer-level packaging process.

Wafer-level packaging can be divided into fan-in type and fan-out type. If the packaged chip size and product size are the same in the two-dimensional plane, the chip has enough area to put all the I/O interfaces into it. Fan-in type will be used.

If the size of the chip is not enough to put down all the I/O interfaces, a fan-out type is needed. Of course, the general fan-out type also adds active and/or passive devices to form SIP while expanding the area.

Fan-out wafer level packaging process flow:

Wafer Preparation and Cutting – Place Wafers in Dicing Tape, Cut into Units to Prepare Metal Carriers – Clean Carriers and Remove All Contaminants

Laminate Bonding – Stimulates adhesive film by pressure

Reconstitute wafers - Pick and place chips from wafers on metal carriers

Molding – Sealing the carrier with mold compound

Remove the carrier plate – remove the molded reconstruction chip from the carrier plate

Arrangement and rewiring – metallization process I/O interface on RDL

Wafer bumps - bumps formed at the I/O external connections

Cut into individual units - cut the molded plastic body

The fan-out package "core" market, including power management and single-chip applications such as RF transceivers, has maintained a stable growth trend. Fan-out package "high-density" market, including applications such as processors and memory, with a larger amount of input and output data, has huge market potential.

Universal Instruments FuzionSC Mounter with Innova Direct Wafer Feeder

Has the following advantages:

Highest Accuracy (±10 μm), Maximum Speed, Maximum Area Assembly

Supports substrates up to 610 mm x 813 mm

Supports placement position compensation by AOI precision feedback

Software supports the assembly of a large number of chips

Precise material handling and heat stage options

The SECS-GEM system can be used to track the wafer

FuzionSC Mounter Two Series

Innova advantages:

Can be directly imported into flip chips and wafer level bare chips for pickup and placement

Can flip chip, bare die and surface mount processes on the same platform

With single wafer feed (Innova), or 13 wafer feeds (Innova +)

No need for upstream wafer sorting

The best solution for system package application

Supports wafers up to 300mm

Support ink and ink-free wafer array mapping

Supports substrates up to 610mm x813mm

Wafer Dilation Depth: Programmable (Innova +), Fixed by Clamp (Innova)

Can be directly imported into flip chip or flip chip

With wafer tracking

The best solution for new product introduction or mass production

Innova direct wafer feeder parameters

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