The purpose of video image encoding/decoding is to convert analog video signals into digital signals for transmission. On the other hand, due to the huge amount of image data obtained by simple video analog-to-digital conversion, image compression technology must be used to reduce data. the amount. There are two implementations in the field of image encoding/decoding. One is based on the implementation of the microcomputer platform. The image data is compressed and encoded by the microcomputer software or by the image processing card based on the microcomputer bus, and can be performed through the PC network. data transmission. Another way is to abandon the microcomputer platform and apply the DSP-based microprocessor algorithm to encode/decode the image. The latter system is called an offline image system. The offline image system has received wide attention due to its small size and flexible application. With the development of micro-processing technology, dedicated image compression/decompression ASIC chips have emerged, and image processing algorithms have been integrated into ASICs, which simplifies the design and implementation of offline image systems.
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Although the dedicated image compression/decompression chip has integrated the encoding/decoding algorithm, the real-time adjustment of the image compression effect, the control of the data rate, and the transmission of the image data still require a high-speed microprocessor to control the implementation. This paper mainly introduces the design and application of high-speed DSP chip TMS320C542 in an offline video image encoding/decoding system from the perspective of hardware design.
1 TMS320C542 peripheral interface function
TMS320C542 is one of the TI's C54x series DSPs. It is a 16-bit fixed-point high-speed micro-processing chip with an operating speed of 40 MIPS, a working voltage of 5 V, and an on-chip RAM of 10 K words, which is a large in-chip RAM in the series. The main peripheral hardware interface functions of C542 are as follows:
Parallel IO interface, including 16-bit address lines and 16-bit data lines. The address line is a unidirectional output pin and the data line is a bidirectional pin. The interface also works with the data area strobe signal DS, the program area strobe signal PS, the IO port strobe signal IS, the data access latch signal MSTRB for memory access, the data latch signal IOSTRB accessed by the IO port, and the read/write signal. R/W.
• 5 external interrupt signal lines, one of which is a non-maskable interrupt, and the remaining 4 are maskable interrupts.
• One program condition jump control input line and one external flag signal output line XF.
Two serial communication signals, one of which is a high-speed serial port BSP with a data buffer, and the other is a time-division multiplexed TDM serial communication port. The data buffer serial port BSP consists of a full-duplex serial interface and a data buffer up to 2K words long. When the buffered transmit/receive mode is used, the data transmission/reception process in the buffer does not affect the DSP running other programs. Code.
· The main control interface HPI is used for data access control between the external processor or the microcomputer bus and the DSP. The external processor or microcomputer can use this interface to access the specified memory space inside the DSP to read or write data without hindering the normal operation of the DSP internal program. Even if the processing speed of the external processor is slow, the HPI interface will not slow down or stop the DSP operation. If it is necessary for the external processor to apply for the DSP service, this port can also be used to trigger the corresponding interrupt of the DSP.
As the core of the offline video encoding/decoding system, the DSP must have high-speed computing capability and hope to provide a good peripheral interface and communication interface. The performance of the C542 meets the needs of the system.
2 DSP peripheral relationship
There are many peripheral devices in the DSP in this system, and each has its own special functions and usages. Therefore, it is the primary problem of system design to straighten out their electrical relationship.
2.1 DSP program loading required peripherals
In addition to the case where the manufacturer directly burns to the on-chip ROM, the C542's running program requires additional devices to help the DSP store the program. After the system power-on reset, the program code is first loaded into the on-chip RAM of the DSP and executed. C54x provides a variety of program loading methods: HPI interface program loading method, 8-bit I/O interface program loading method, 16-bit I/O interface program loading method, 8-bit parallel EPROM program loading method, 16-bit parallel EPROM program loading Method and serial program loading method. The system chooses to use a 32K×8bit EPROM to load the program into the DSP by using the 8-bit parallel ERTPM program loading method.
After the power-on report, the DSP first reads the data SRC whose IO port address is OFFFFh. The lowest two bits of the 16-bit data SRC, bit 1-0, determine the program download method selected by the user. When these two bits are 01, the 8-bit parallel EPROM program loading method can be selected. Then, the result of multiplying the bit 7-2 bit data of SRC by 2 10 will be used as the starting address of the DSP access EPROM. Thereafter, the DSP will load the data area from the start address of the program code into the program area for execution.
The system uses a 32K×8bit EPROM as a data space storage loader with a starting address of 8000h. At this time, bits 7 to 0 of the SRC should be set to 10000001. According to the CMOS circuit specification, the system uses a 4.7kΩ resistor to pull the 0th and 7th bits of the DSP data line to a high level, and the 1st to 6th bits of the data line are pulled down to ground with a 4.7kΩ resistor. The use of resistors makes it possible to prevent the correct logic on the data lines when the device drives the data bus. On the other hand, when the DSP accesses the IO port of 0FFFFh, the DSP can read the correct one as long as the other chips release the data bus. SRC data.
2.2 Dedicated video image encoding/decoding ASIC
The dedicated video image encoding/decoding ASIC provides a 16-bit data interface that allows access to data from different internal registers of the ASIC through four address lines. Through this interface, the DSP can set the working state of the video image encoding/decoding and the image compression effect. Through this interface, the DSP can also read relevant statistics of the image, such as the total brightness of the image, the maximum brightness and minimum brightness of the pixel, etc., in order to provide a basis for the DSP to adjust the compression effect. Through this interface, it is also possible to read compressed image data or write compressed image data. At this time, the interface is equivalent to a FIFO interface, and the dedicated video encoding/decoding ASIC can actively issue a service request interrupt and apply for data to the DSP. Access and control processing.
According to the interface characteristics of this dedicated video encoding/decoding ASIC, the system utilizes the IO port of the DSP to access and process the peripheral device.
2.3 low speed control microcontroller
DSP as a high-speed arithmetic processor is not suitable for low-speed control applications. In this system, the adjustment of image brightness, chromaticity and contrast, the control of the camera pan/tilt, the reception of the signal of the user controller and the display of the indicator of the working status of the system are some low-speed controls. This system uses a single-chip microcomputer to complete these tasks, which also requires the DSP and the microcontroller to exchange control commands.
The C542's HPI interface provides a good solution for communication between the DSP and the microcontroller. Although the 8 data lines and 5 access control lines of the HPI interface occupy 13 IO pins of the microcontroller, the IO resources of all the microcontrollers in this system are sufficient. With the HPI interface, the microcontroller can send user commands to the DSP and request DSP processing by initiating a DSP interrupt. The DSP can also request the microcontroller to perform the corresponding operation through the HPI interface. With the characteristics of the HPI interface, the communication between the two microprocessors does not have to match the data transmission rate, nor does it affect the execution speed of the respective programs.
2.4 Image Data Storage SRAM
In order to achieve flow rate control of data transmission, memory buffer data is required. At the same time, to achieve image freeze and other processing functions, it also requires sufficient storage space. This system selects 128K×16bit high-speed SRAM to expand the limited storage space of C542. The internal RAM of C542 occupies the data area with the address from 0000 to 27FFh, and the data area of ​​8000~0FFFFh has been allocated to the EPROM placement program code. Finally, only the address of 2800~7FFFh can be used for SRAM. One solution for extending the SRAM access address line is to use two addressing methods. The first time, the partial address is given and cached, and the data is not accessed at this time; on the second access, the remaining address data is given, and then the spliced ​​total address is used to access the data.
Since the image data is a data stream, its storage and reading in the SRAM are sequential increments of addresses. According to this feature, the system designed a new SRAM address line expansion method. The method divides every 32 16-bit word image data into a minimum unit group of data operations. The 32-word data is the same in the upper 12 bits of the address stored in the SRAM. This high 12-bit address is selected using the lower 12-bit address line of the DSP. The lower 5 bits of the SRAM are automatically incremented by a 5-bit binary counter. That is, each time a high 12-bit address is accessed, the lower address is automatically incremented by 1. Thus, only 12 address lines of the DSP are actually used, and the access can be efficiently accessed. All storage space for SRAM. Finally, the upper four bits A15~12 of the DSP address line should select two values ​​between 0011 and 0111, one for chip select SRAM and one for reset counter.
2.5 Data Communication High Speed ​​Serial Port
The system directly uses the buffered serial port BSP of the C542 as the communication interface that the system opens to the user. The interface has a data rate of up to 40 Mbps and the length of the packet can be selected from 8 bits, 10 bits, 12 bits and 16 bits. The BSPR operation of the receiving part of the BSP serial port is in the passive mode, and the clock and frame synchronization signals accompanying the received data should be provided externally. The BSPX of the BSP serial port can work in active mode, and its data clock and frame synchronization are provided internally by the DSP. The BSPX can also work in passive mode, with the data clock and frame sync clock being externally input. The BSP's buffer data is automatically sent and received, which also simplifies the processing of the DSP. The system adds interface driver to the BSP serial port of DSP, which constitutes the communication interface of the system.
3 DSP part of the system design
Figure 1 is the schematic diagram of the core DSP part of the offline video encoding/decoding system. The DSP serial buffer DSP constitutes the user communication serial port separately. The DSP's HPI interface realizes the communication between the DSP and the low-speed control MCU. The remaining peripherals connected to the IO interface of the DSP are power-on reset SRC data logic, program load EPROM, video image code/decode ASIC, and image data storage SRAM. EPROM and SRAM are handled as DSP extended data storage areas, and SRC data logic and video encoding/decoding ASICs are accessed as DSP IO ports. From the perspective of program instructions, data memory access operations should use DSP data access instructions, such as LD, ST, MVDD, etc., while IO port access uses the DSP's IO port access instructions PORTR and PORTW.
The 16-bit data line and the 16-bit address line of the IO interface of the DSP constitute the data bus and address bus of the peripheral device. Small-scale MACH programmable logic devices are used to design access control logic for IO peripherals. The chip select and read and write signals of each device generated by the MACH are determined by its relationship to the DSP, its addressing range, and the characteristics of the pin signals. For example, the program download EPROM is the extended data area of ​​the DSP, and the addressing range is 8000~0FFFFh. If its chip select signal is active high, the EPROM chip select logic is:
CS-EPROM=(!DS)&A15
When the DSP accesses the data area, DS is active, low, and when the highest bit A15 of the address line is 1, the CS_EPROM signal is valid and the EPROM is strobed. In addition, the binary five-bit counter for SRAM access address auto-increment is also implemented by the MACH programmable logic device, which constructs an additional five address lines.
By utilizing the DSP and HPI interface functions of the DSP chip TMS320C542, and combining the MACH programmable logic chip to extend the IO interface function of the DSP, the offline video chip is extended to the IO interface function of the DSP, thereby realizing the offline logic chip expansion. The IO interface function of the DSP realizes the design of the control core of the offline video image encoding/decoding system. Through actual debugging, the DSP can correctly download and run the program code from the EPROM during power-on reset. The DSP can correctly access the video encoding/decoding ASIC and data storage SRAM, and the command data exchange and serial port data transmission between the DSP and the microcontroller. Can be implemented normally. This well-structured and compact hardware design provides convenience for further software development. DSP's instruction code for peripheral data access, especially for SRAM, is simple and efficient, which saves valuable instruction cycle resources for other image real-time control algorithms in DSP program software.
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