From the core modules of the network to the edge devices, they are undergoing tremendous changes. The wireless market's tens of millions of "always on" connections, the tremendous transmission pressure of next-generation backhaul communications, and various broadband communications for consumers using existing wired communications infrastructure are key factors driving network development. . As a result, the network core is moving toward 100 and 400 Gbps data channels; the network center area is also being upgraded from 10 Gbps to 100 Gbps to support the ever-expanding variety of network access standards, protocols and interfaces. In addition, to support the increasing user traffic demands and reduce overall transmission delays, access networks are also being upgraded from previous parallel interfaces to modern high-speed serial interfaces.
As network operators expect to increase network capacity at a lower cost while maintaining overall coverage, it is often impossible to completely replace the currently installed hardware. Product launch time, overall upgrade costs, and investment in existing software support are just a few of the issues that must be considered. When a device is upgraded, it must provide the necessary "refurbishment" to extend the lifespan and add features that meet the expected network requirements. Many NEPs (network equipment vendors) find that mid-range FPGAs with transceiver capabilities are very effective. solution.
Mid-range FPGAs are a relatively new class of FPGAs. These cost- and power-optimized devices offer all the features of a traditional field-programmable gate array combined with advanced features that are only available in high-end devices. For example, these programmable devices offer cost-effective and power-optimized serial interfaces (SERDES) that enable them to bridge the gap between existing and next-generation communication solutions. Mid-range FPGAs with serial interfaces can also be configured to support a variety of data transfer rates and interface standards, whether industry-standard or proprietary. And because devices of the same size are unlikely to meet all of the requirements, the number of SERDES channels for these devices varies from model to model, allowing designers to optimize their programmable solutions to meet specific cost and power goals. .
The configurable capabilities of the serial interface in midrange FPGAs are critical, giving them a unique competitive advantage. While many network equipment vendors in the past may consider adopting their "self-developed" interface standards, especially if the entire rack of equipment has been developed by the same manufacturer, today's market has a variety of options, and suppliers Interoperability between devices has become inevitable. Large system vendors will continue to offer complete solutions, while other manufacturers seek differentiated solutions that work within industry-standard chassis, or stand-alone “thin devicesâ€. Implementing industry-standard serial interfaces not only reduces system design time, but also improves interoperability between different vendors, increases overall system reliability, and broadens the reach of vendor equipment.
An important feature when implementing a serial interface is the ability to create scalable data links to meet the transmission bandwidth requirements. To match the bandwidth to the supported transport protocols, mid-range FPGAs incorporate hardened PMA and PCS logic blocks that are functionally bonded together. The bonding mechanism implements multiple transceiver channels to support one protocol, while the remaining serial interfaces can still support other protocols independently or be disabled, further saving overall system power consumption. While the transceiver provides a physical layer interface by adding PMA and PCS functional blocks, it also requires a large amount of additional logic at the higher "customer" level to create a complete industry standard solution. While ASSPs can provide specific interface solutions with hardened serial interfaces, they lack the necessary flexibility to support the various interfaces used in the network access market.
In addition, high-end FPGAs based on SERDES can also be designed to contain a large amount of serial transfer logic within their structure, at a cost: additional design and verification time, more power and size. In addition, midrange FPGAs offer another key advantage for board and system level designers. By adding a certain number of transceivers (depending on the device) to the soft logic array of the FPGA, as well as hardened industry standard transport protocol logic, these devices provide a flexible, low cost and small size communication solution. As shown in Figure 1, different transport protocol solutions can be easily implemented by selecting the appropriate FPGA.
Figure 1: Mid-range FPGA with transceiver capability
The access network consists of infrastructure equipment from different network operators. And, as a large number of obsolete devices are expected to continue to be used in the next few years, more and more operators are turning to an all-packet network. With the development of full packet networks, some industry standard technologies are rapidly becoming the dominant control platform and data transmission interconnect. With its long history, extensive use, and support for local IP packets, Ethernet will dominate the next generation of networks. PCI-Express, which is widely used in the computing, server, and consumer electronics markets, is also being used extensively for device-level and back-plane interconnects, and is also widely deployed to replace parallel PCI buses. The Serial Wireless IO standard is used in a variety of wireless, DSP and other embedded computing solutions. As mentioned above, many midrange FPGAs support these key standards, providing device manufacturers with a rich set of hardening solutions. In addition to cost and power advantages, these devices do not require implementation and verification of communication protocols, allowing designers to focus on implementing their own differentiated solutions and system upgrades within the FPGA fabric.
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