Jan Gray is an expert in integrating 32-bit RISC processors in FPGAs. He wrote a blog called FPGA CPU News, subtitled "Developing Parallel Computer Architecture with FPGAs." Jan Gray's latest post is FPGAs, then and now, this post compares the integration of the J32 32-bit RISC CPU in the Xilinx XC4010PC84-5 FPGA with the current Xilinx Virtex-7 XC7VX690T FPGA in 1995. Gray uses a J32 processor with a classic RISC architecture with 3-operand operation instructions, 4=stage pipeline (extract, register read, execute, write back), and a 32-bit operand register file.
In 1995, the J32 processor used by Gray basically consumed 800 4-input LUTs in the XC4010 FPGA. The processor arrangement looks like this:
13 years later. The same J32 processor core is integrated into the Virtex-7 FPGA, which supports more than 433,000 6-input LUTs, which is 1000 times the space reserved for 250 router cores and 1000 processors. The arrangement of the J32 RISC processor looks like this:
“That is to say, Moore's Law has upgraded each FPGA-integrated 1K LUT to an FPGA-integrated 1K 32-bit CPU over the past 18 years. (By the way, the largest Virtex Ultrascale 3D FPGA has 4.4 million logic cells, so the logical capacity More than 10,000 32-bit RISC J32 CPUs mentioned by Jan Gray are interconnected. See the note below !)
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